16.3 关键模块（续）文件：image_processor_system.vmodule image_processor_system ( // 摄像头接口 input wire clk_camera, input wire [7:0] pixel_in, input wire pixel_valid, // 显示器接口 input wire clk_display, output wire [7:0] pixel_out, output wire pixel_valid_out, // 控制接口 input wire reset, input wire [3:0] filter_mode, // 状态输出 output wire [3:0] status_led ); // 内部信号 wire [7:0] input_fifo_data; wire input_fifo_valid; wire input_fifo_ready; wire [7:0] processor_data; wire processor_valid; wire [7:0] output_fifo_data; wire output_fifo_valid; wire output_fifo_ready; // 1. 输入FIFO（摄像头时钟域） fif